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DAC
1997
ACM
14 years 14 days ago
Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT
We describe an architectural design space exploration methodology that minimizes the energy dissipation of digital circuits. The centerpiece of our methodology is a Verilog-based ...
Thucydides Xanthopoulos, Yoshifumi Yaoi, Anantha C...
ARCS
2006
Springer
14 years 14 hour ago
Minimising the Hardware Resources for a Cellular Automaton with Moving Creatures
: Given is the following "creature's exploration problem": n creatures are moving around in an unknown environment in order to visit all cells in shortest time. This...
Mathias Halbach, Rolf Hoffmann
WSC
2007
13 years 10 months ago
Supporting parametrization of business games for multiple educational settings
The parametrization of business games benefits from the usage of a multi-tier architecture and software services. This paper shows that the multi-tier concept supports parametriz...
Stijn-Pieter A. van Houten, Alexander Verbraeck
CORR
2004
Springer
142views Education» more  CORR 2004»
13 years 8 months ago
Modeling and Validating Hybrid Systems Using VDM and Mathematica
Hybrid systems are characterized by the hybrid evolution of their state: A part of the state changes discretely, the other part changes continuously over time. Typically, modern c...
Bernhard K. Aichernig, Reinhold Kainhofer
DSD
2007
IEEE
160views Hardware» more  DSD 2007»
14 years 2 months ago
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
Scott Miller, Mihai Sima, Michael McGuire