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INFOCOM
2009
IEEE
14 years 2 months ago
Circuits/Cutsets Duality and a Unified Algorithmic Framework for Survivable Logical Topology Design in IP-over-WDM Optical Netwo
: Given a logical topology and a physical topology , the survivable logical topology design problem in an IP-overWDM optical network is to map the logical links into lightpaths in ...
Krishnaiyan Thulasiraman, Muhammad S. Javed, Guoli...
DAC
2005
ACM
14 years 9 months ago
Designing logic circuits for probabilistic computation in the presence of noise
As Si CMOS devices are scaled down into the nanoscale regime, current computer architecture approaches are reaching their practical limits. Future nano-architectures will confront...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
ISQED
2007
IEEE
136views Hardware» more  ISQED 2007»
14 years 2 months ago
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS
Straining of silicon improves mobility of carriers resulting in speed enhancement for transistors in CMOS technology. Traditionally, silicon straining is applied in a similar ad-h...
Rajani Kuchipudi, Hamid Mahmoodi
KR
1991
Springer
13 years 11 months ago
Meta-Reasoning in Executable Temporal Logic
Temporal logic can be used as a programming language. If temporal formulae are represented in the form of an implication where the antecedent refers to the past, and the consequen...
Howard Barringer, Michael Fisher, Dov M. Gabbay, A...
QEST
2007
IEEE
14 years 2 months ago
Qualitative Logics and Equivalences for Probabilistic Systems
We investigate logics and equivalence relations that capture the qualitative behavior of Markov Decision Processes (MDPs). We present Qualitative Randomized Ctl (Qrctl): formulas o...
Luca de Alfaro, Krishnendu Chatterjee, Marco Faell...