1010 search results - page 8 / 202 » Logics for Contravariant Simulations |
FORMATS
2006
Springer
13 years 11 months ago
2006
Springer
In this paper, we consider a novel approach to the temporal logic verification problem of continuous dynamical systems. Our methodology has the distinctive feature that enables the...
DAC
1999
ACM
14 years 7 days ago
1999
ACM
This paper describes a two-state methodology for register transfer level (RTL) logic simulation in which the use of the Xstate is completely eliminated inside ASIC designs. Exampl...
TCAD
2008
13 years 7 months ago
2008
The relatively poor scaling of interconnect in modern digital circuits necessitates a number of design optimizations, which must typically be iterated several times to meet the spe...
KES
2005
Springer
14 years 1 months ago
2005
Springer
This paper presents a system for recognizing sketched logic circuits in real-time and graphically simulating them afterwords. It has been developed for use in university and school...
ICCD
1993
IEEE
14 years 2 days ago
1993
IEEE
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...