2501 search results - page 491 / 501 » Logics with Rank Operators |
CAISE
2006
Springer
13 years 11 months ago
2006
Springer
Abstract. We discuss a case study for the hospital scenario where workflow model components are distributed across various computers or devices (e.g. mobile phones, PDAs, sensors, ...
FCCM
2004
IEEE
13 years 11 months ago
2004
IEEE
Reconfigurable System-on-Chip (SoC) platforms that incorporate hard-core processors surrounded by large amounts of FPGA are today commodities: the reconfigurable logic is often us...
ASPDAC
1995
ACM
13 years 11 months ago
1995
ACM
- In this paper, we present a new scheduling algorithms that generates area-efficient register transfer level datapaths with multiport memories. The proposed scheduling algorithm a...
FPGA
1995
ACM
13 years 11 months ago
1995
ACM
In this paper, we present an improvement of the FlowMap algorithm, named CutMap, which combines depth and area minimization in the mapping process by computing min-cost min-height...
HIPEAC
2009
Springer
13 years 10 months ago
2009
Springer
Shrinking process technologies and growing chip sizes have profound effects on process variation. This leads to Chip Multiprocessors (CMPs) where not all cores operate at maximum f...