114 search results - page 20 / 23 » Loop Parallelization in the Polytope Model |
IPPS
2003
IEEE
14 years 27 days ago
2003
IEEE
Most evolutionary approaches to fault recovery in FPGAs focus on evolving alternative logic configurations as opposed to evolving the intra-cell routing. Since the majority of tra...
CGO
2010
IEEE
14 years 2 months ago
2010
IEEE
Tiling is a widely used loop transformation for exposing/exploiting parallelism and data locality. Effective use of tiling requires selection and tuning of the tile sizes. This is...
VLSID
2007
IEEE
14 years 8 months ago
2007
IEEE
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...
COCO
2007
Springer
14 years 1 months ago
2007
Springer
We study a model of graph related formulae that we call the Constraint-Graph model. A constraintgraph is a labeled multi-graph (a graph where loops and parallel edges are allowed)...
ICS
2005
Tsinghua U.
14 years 1 months ago
2005
Tsinghua U.
A key step in program optimization is the determination of optimal values for code optimization parameters such as cache tile sizes and loop unrolling factors. One approach, which...