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CGO
2004
IEEE
13 years 10 months ago
Custom Data Layout for Memory Parallelism
In this paper, we describe a generalized approach to deriving a custom data layout in multiple memory banks for array-based computations, to facilitate high-bandwidth parallel mem...
Byoungro So, Mary W. Hall, Heidi E. Ziegler
DATE
2009
IEEE
149views Hardware» more  DATE 2009»
14 years 1 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh...
SAMOS
2004
Springer
13 years 12 months ago
High-Speed Event-Driven RTL Compiled Simulation
In this paper we present a new approach for generating high-speed optimized event-driven register transfer level (RTL) compiled simulators. The generation of the simulators is part...
Alexey Kupriyanov, Frank Hannig, Jürgen Teich
ATS
1998
IEEE
170views Hardware» more  ATS 1998»
13 years 11 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...
ICSM
1999
IEEE
13 years 11 months ago
A Two-Phase Process for Software Architecture Improvement
Software architecture is important for large systems in which it is the main means for, among other things, controlling complexity. Current ideas on software architectures were no...
René L. Krikhaar, André Postma, M. P...