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IPPS
2007
IEEE
14 years 4 months ago
A Portable Framework for High-Speed Parallel Producer/Consumers on Real CMP, SMT and SMP Architectures
This paper explores generating efficient, portable HighSpeed Producer Consumer (HSPC) code on current shared memory architectures: Chip Multi-Processors (CMP), Simultaneous Multi...
Richard T. Saunders, Clinton L. Jeffery, Derek T. ...
RSP
2006
IEEE
120views Control Systems» more  RSP 2006»
14 years 3 months ago
A Case Study of Design Space Exploration for Embedded Multimedia Applications on SoCs
Embedded real-time multimedia applications usually imply data parallel processing. SIMD processors embedded in SOCs are cost-effective to exploit the underlying parallelism. Howev...
Isabelle Hurbain, Corinne Ancourt, François...
CODES
2000
IEEE
14 years 2 months ago
Co-design of interleaved memory systems
Memory interleaving is a cost-efficient approach to increase bandwidth. Improving data access locality and reducing memory access conflicts are two important aspects to achieve hi...
Hua Lin, Wayne Wolf
SIGCOMM
2005
ACM
14 years 3 months ago
Using redundancy to cope with failures in a delay tolerant network
We consider the problem of routing in a delay tolerant network (DTN) in the presence of path failures. Previous work on DTN routing has focused on using precisely known network dy...
Sushant Jain, Michael J. Demmer, Rabin K. Patra, K...
ISVLSI
2008
IEEE
118views VLSI» more  ISVLSI 2008»
14 years 4 months ago
MPI-Based Adaptive Task Migration Support on the HS-Scale System
Scalability of architecture, programming model and task control management will be a major challenge for future VLSI systems. In this context, homogeneous MPSOC is a seducing appr...
Nicolas Saint-Jean, Pascal Benoit, Gilles Sassatel...