Sciweavers

87 search results - page 8 / 18
» Low Energy, Highly-Associative Cache Design for Embedded Pro...
Sort
View
ISCAPDCS
2008
13 years 8 months ago
Parallel Embedded Systems: Where Real-Time and Low-Power Meet
This paper introduces a combination of models and proofs for optimal power management via Dynamic Frequency Scaling and Dynamic Voltage Scaling. The approach is suitable for syste...
Zdravko Karakehayov, Yu Guo
DAC
1999
ACM
14 years 8 months ago
Cycle-Accurate Simulation of Energy Consumption in Embedded Systems
This paper presents a methodology for cycle-accurate simulation of energy dissipation in embedded systems. The ARM Ltd. 1 instruction-level cycle-accurate simulator is extended wi...
Tajana Simunic, Luca Benini, Giovanni De Micheli
SBCCI
2005
ACM
115views VLSI» more  SBCCI 2005»
14 years 27 days ago
Design of a decompressor engine on a SPARC processor
Code compression, initially conceived as an effective technique to reduce code size in embedded systems, today also brings advantages in terms of performance and energy consumpti...
Richard E. Billo, Rodolfo Azevedo, Guido Araujo, P...
CF
2011
ACM
12 years 7 months ago
Hybrid high-performance low-power and ultra-low energy reliable caches
Ubiquitous computing has become a very popular paradigm. The most suitable technological solution for those systems consists of using hybrid processors able to operate at high vol...
Bojan Maric, Jaume Abella, Francisco J. Cazorla, M...
ISLPED
2003
ACM
115views Hardware» more  ISLPED 2003»
14 years 18 days ago
Reducing energy and delay using efficient victim caches
In this paper, we investigate methods for improving the hit rates in the first level of memory hierarchy. Particularly, we propose victim cache structures to reduce the number of ...
Gokhan Memik, Glenn Reinman, William H. Mangione-S...