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VLSID
2007
IEEE
210views VLSI» more  VLSID 2007»
14 years 7 months ago
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
Phillip H. Jones, Young H. Cho, John W. Lockwood
MICRO
2009
IEEE
99views Hardware» more  MICRO 2009»
14 years 2 months ago
Low-cost router microarchitecture for on-chip networks
On-chip networks are critical to the scaling of future multicore processors. The challenge for on-chip network is to reduce the cost including power consumption and area while pro...
John Kim
MICRO
2008
IEEE
131views Hardware» more  MICRO 2008»
14 years 1 months ago
Token flow control
As companies move towards many-core chips, an efficient onchip communication fabric to connect these cores assumes critical importance. To address limitations to wire delay scala...
Amit Kumar 0002, Li-Shiuan Peh, Niraj K. Jha
IPPS
2006
IEEE
14 years 1 months ago
Compiler assisted dynamic management of registers for network processors
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
R. Collins, Fernando Alegre, Xiaotong Zhuang, Sant...
OTM
2009
Springer
14 years 1 months ago
Semantic Event Correlation Using Ontologies
Complex event processing (CEP) is a software architecture paradigm that aims at low latency, high throughput, and quick adaptability of applications for supporting and improving ev...
Thomas Moser, Heinz Roth, Szabolcs Rozsnyai, Richa...