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GLVLSI
2007
IEEE
158views VLSI» more  GLVLSI 2007»
15 years 8 months ago
RT-level vector selection for realistic peak power simulation
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
Chia-Chien Weng, Ching-Shang Yang, Shi-Yu Huang
MICRO
2002
IEEE
117views Hardware» more  MICRO 2002»
15 years 5 months ago
Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction
On-chip caches represent a sizeable fraction of the total power consumption of microprocessors. Although large caches can significantly improve performance, they have the potentia...
Nam Sung Kim, Krisztián Flautner, David Bla...
SI3D
1999
ACM
15 years 10 months ago
Applications of pixel textures in visualization and realistic image synthesis
With fast 3D graphics becoming more and more available even on low end platforms, the focus in developing new graphics hardware is beginning to shift towards higher quality render...
Wolfgang Heidrich, Rüdiger Westermann, Hans-P...
SBCCI
2005
ACM
111views VLSI» more  SBCCI 2005»
15 years 11 months ago
Total leakage power optimization with improved mixed gates
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
Frank Sill, Frank Grassert, Dirk Timmermann
VTC
2007
IEEE
16 years 14 days ago
Discrete Power Allocation for Lifetime Maximization in Cooperative Networks
Abstract— Discrete power allocation strategies for amplifyand-forward cooperative networks are proposed based on selective relaying methods. The goal of power allocation is to ma...
Wan-Jen Huang, Yao-Win Hong, C. C. Jay Kuo