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ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
14 years 2 months ago
A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management
An energy efficient object recognition processor is proposed for real-time visual applications. Its energy efficiency is improved by lowering average power consumption while susta...
Joo-Young Kim, Seungjin Lee, Jinwook Oh, Minsu Kim...
ASPDAC
2007
ACM
93views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Flow-Through-Queue based Power Management for Gigabit Ethernet Controller
- This paper presents a novel architectural mechanism and a power management structure for the design of an energy-efficient Gigabit Ethernet controller. Key characteristics of suc...
Hwisung Jung, Andy Hwang, Massoud Pedram
CODES
2007
IEEE
13 years 11 months ago
Energy efficient co-scheduling in dynamically reconfigurable systems
Energy consumption is a major issue in dynamically reconfigurable systems because of the high power requirements during repeated configurations. Hardware designs employ low power ...
Pao-Ann Hsiung, Pin-Hsien Lu, Chih-Wen Liu
ICCD
2004
IEEE
114views Hardware» more  ICCD 2004»
14 years 4 months ago
Low Energy, Highly-Associative Cache Design for Embedded Processors
Many embedded processors use highly associative data caches implemented using a CAM-based tag search. When high-associativity is desirable, CAM designs can offer performance advan...
Alexander V. Veidenbaum, Dan Nicolaescu
ISCAS
2008
IEEE
115views Hardware» more  ISCAS 2008»
14 years 2 months ago
FSMD partitioning for low power using simulated annealing
— It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partiti...
Nainesh Agarwal, Nikitas J. Dimopoulos