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112
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ISLPED
2009
ACM
168views Hardware» more  ISLPED 2009»
15 years 10 months ago
A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management
An energy efficient object recognition processor is proposed for real-time visual applications. Its energy efficiency is improved by lowering average power consumption while susta...
Joo-Young Kim, Seungjin Lee, Jinwook Oh, Minsu Kim...
113
Voted
ASPDAC
2007
ACM
93views Hardware» more  ASPDAC 2007»
15 years 7 months ago
Flow-Through-Queue based Power Management for Gigabit Ethernet Controller
- This paper presents a novel architectural mechanism and a power management structure for the design of an energy-efficient Gigabit Ethernet controller. Key characteristics of suc...
Hwisung Jung, Andy Hwang, Massoud Pedram
128
Voted
WWIC
2005
Springer
137views Communications» more  WWIC 2005»
15 years 9 months ago
Providing Delay Guarantees and Power Saving in IEEE 802.11e Network
Recently, the 802.11e Working Group (WG) has proposed the Hybrid Coordination Function (HCF), which has a HCF Controlled Channel Access (HCCA) and an Enhanced Distributed Coordinat...
Gennaro Boggia, Pietro Camarda, F. A. Favia, Luigi...
105
Voted
IBMRD
2006
63views more  IBMRD 2006»
15 years 3 months ago
Decomposing the load-store queue by function for power reduction and scalability
Because they are based on large content-addressable memories, load-store queues (LSQ) present implementation challenges in superscalar processors, especially as issue width and nu...
Lee Baugh, Craig B. Zilles
124
Voted
DATE
2006
IEEE
176views Hardware» more  DATE 2006»
15 years 9 months ago
Low power synthesis of dynamic logic circuits using fine-grained clock gating
— Clock power consumes a significant fraction of total power dissipation in high speed precharge/evaluate logic styles. In this paper, we present a novel low-cost design methodol...
Nilanjan Banerjee, Kaushik Roy, Hamid Mahmoodi-Mei...