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ASPDAC
2006
ACM
116views Hardware» more  ASPDAC 2006»
15 years 10 months ago
Abridged addressing: a low power memory addressing strategy
Abstract— The memory subsystem is known to comprise a significant fraction of the power dissipation in embedded systems. The memory addressing strategy, which determines the seq...
Preeti Ranjan Panda
ISQED
2000
IEEE
131views Hardware» more  ISQED 2000»
15 years 8 months ago
Low Power Testing of VLSI Circuits: Problems and Solutions
Power and energy consumption of digital systems may increase significantly during testing. This extra power consumption due to test application may give rise to severe hazards to ...
Patrick Girard
SBCCI
2009
ACM
187views VLSI» more  SBCCI 2009»
15 years 8 months ago
Design of low complexity digital FIR filters
The multiplication of a variable by multiple constants, i.e., the multiple constant multiplications (MCM), has been a central operation and performance bottleneck in many applicat...
Levent Aksoy, Diego Jaccottet, Eduardo Costa
HPCN
1997
Springer
15 years 8 months ago
High Performance Simulation for Resonant-Mass Gravitational Radiation Antennas
Abstract. In this paper the design and validation of a high performance simulation is discussed that is of critical value to the feasibility study of the GRAIL project, the aim of ...
Jan F. de Ronde, G. Dick van Albada, Peter M. A. S...
IWANN
2005
Springer
15 years 9 months ago
Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures
Abstract. In this paper we analyse a serial (ripple carry) and a parallel (Kogge-Stone) adder when operating in subthreshold at 100nm and 70nm. These are targeted for ultra low pow...
Valeriu Beiu, Asbjørn Djupdal, Snorre Aunet