3799 search results - page 72 / 760 » Low Power or High Performance |
136
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GLVLSI
2007
IEEE
15 years 5 months ago
2007
IEEE
We present a vector selection methodology for estimating the peak power dissipation in a CMOS logic circuit. The ultimate goal is to combine the speed of RT-level simulation with ...
147
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ASPDAC
2009
ACM
15 years 10 months ago
2009
ACM
Low power circuits have become a necessary part in modern designs. Retention flip-flop is one of the most important components in low power designs. Conventional test methodologie...
157
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TVLSI
2008
15 years 3 months ago
2008
Chip-Multi-Processors (CMP) utilize multiple energy-efficient Processing Elements (PEs) to deliver high performance while maintaining an efficient ratio of performance to energy-c...
151
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CASES
2006
ACM
15 years 10 months ago
2006
ACM
We propose an architecture that uses NAND flash memory to reduce main memory power in web server platforms. Our architecture uses a two level file buffer cache composed of a re...
138
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ASPDAC
2008
ACM
15 years 6 months ago
2008
ACM
Traditionally, clock network layout is performed after cell placement. Such methodology is facing a serious problem in nanometer IC designs where people tend to use huge clock buff...