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VLSID
1993
IEEE
234views VLSI» more  VLSID 1993»
15 years 8 months ago
NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs
High throughput and low latency designs are required in modern high performance systems, especially for signal processing applications. Existing logic families cannot provide both...
Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V....
ISCA
2007
IEEE
168views Hardware» more  ISCA 2007»
15 years 10 months ago
Limiting the power consumption of main memory
The peak power consumption of hardware components affects their power supply, packaging, and cooling requirements. When the peak power consumption is high, the hardware components...
Bruno Diniz, Dorgival Olavo Guedes Neto, Wagner Me...
VLSID
2007
IEEE
104views VLSI» more  VLSID 2007»
16 years 4 months ago
Customization of Register File Banking Architecture for Low Power
Register file banking is an effective alternative to monolithic register files in embedded processor based systems. In this work, we propose techniques for performing application s...
Rakesh Nalluri, Rohan Garg, Preeti Ranjan Panda
WIOPT
2010
IEEE
15 years 2 months ago
Low complexity algorithms for relay selection and power control in interference-limited environments
Abstract—We consider an interference-limited wireless network, where multiple source-destination pairs compete for the same pool of relay nodes. In an attempt to maximize the sum...
Lazaros Gkatzikis, Iordanis Koutsopoulos
VLSID
2007
IEEE
128views VLSI» more  VLSID 2007»
16 years 4 months ago
A Low Power Frequency Multiplication Technique for ZigBee Transciever
A low-power frequency multiplication technique, developed for ZigBee (IEEE 802.15.4) like applications is presented. We have provided an estimate for the power consumption for a g...
Jagdish Nayayan Pandey, Sudhir S. Kudva, Bharadwaj...