A Low Power Frequency Multiplication Technique for ZigBee Transciever

A low-power frequency multiplication technique, developed for ZigBee (IEEE 802.15.4) like applications is presented. We have provided an estimate for the power consumption for a given output voltage swing using our technique. The advantages and disadvantages which determine the application areas of the technique are discussed. The issues related to design, layout and process variation are also addressed. Finally, a design is presented for operation in 2.405--2.485-GHz band of ZigBee receiver. SpectreRF simulations show 30% improvement in efficiency for our circuit with regard to conversion of DC bias current to output amplitude, against a LCVCO. To establish the low-power credentials, we have compared our circuit with an existing technique; our circuit performs better with just 1/3 of total current from supply, and uses one inductor as against three in the latter case. A test chip was implemented in UMC 0.13-?m RF process with spiral on-chip inductors and MIM (Metal-Insulator-Metal) c...

• Type: Conference
• Year: 2007
• Where: VLSID
• Authors: Jagdish Nayayan Pandey, Sudhir S. Kudva, Bharadwaj Amrutur
• Keywords: Computer Architecture, Frequency Multiplication Technique, Low-power Credentials, Spiral On-chip Inductors, VLSID 2007