3799 search results - page 99 / 760 » Low Power or High Performance |
133
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GLOBECOM
2007
IEEE
15 years 10 months ago
2007
IEEE
— Optimal pilot design and placement for channel estimation in Multiple-input Multiple-output (MIMO) Orthogonal Frequency-Division Multiplexing (OFDM) systems in the presence of ...
143
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ICCD
2007
IEEE
16 years 1 months ago
2007
IEEE
Our objective was to determine the most energy efficient 64b static CMOS adder architecture, for a range of high-performance delay targets. We examine extensively carry-lookahead ...
150
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SAMOS
2007
Springer
15 years 10 months ago
2007
Springer
When peak performance is unnecessary, Dynamic Voltage Scaling (DVS) can be used to reduce the dynamic power consumption of embedded multiprocessors. In future technologies, however...
140
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DAC
1997
ACM
15 years 8 months ago
1997
ACM
Multi-threshold CMOS is an increasingly popular circuit approach that enables high performance and low power operation. However, no methodologies have been developed to size the h...
121
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ASPDAC
2005
ACM
15 years 6 months ago
2005
ACM
Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they cons...