240 search results - page 22 / 48 » Low energy asynchronous architectures |
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
Abstract—Recent breakthroughs in circuit and process technology have enabled new usage models for non-volatile memory technologies such as Flash and phase change RAM (PCRAM) in t...
JSA
2000
13 years 7 months ago
2000
Portable products are being used increasingly. Because these systems are battery powered, reducing power consumption is vital. In this report we give the properties of low power d...
LCTRTS
2007
Springer
14 years 1 months ago
2007
Springer
Set-associative caches are traditionally managed using hardwarebased lookup and replacement schemes that have high energy overheads. Ideally, the caching strategy should be tailor...
HPCA
2005
IEEE
14 years 8 months ago
2005
IEEE
A large multi-ported register file is indispensable for exploiting instruction level parallelism (ILP) in today's dynamically scheduled superscalar processors. The number of ...
ICCD
2004
IEEE
14 years 4 months ago
2004
IEEE
This paper proposes a power-aware cache block allocation algorithm for the way-selective setassociative cache on embedded systems to reduce energy consumption without additional d...