240 search results - page 33 / 48 » Low energy asynchronous architectures |
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
ASAP
2010
IEEE
13 years 9 months ago
2010
IEEE
In a traditional Network-on-Chip (NoC), latency and power dissipation increase with system size due to its inherent multi-hop communications. The performance of NoC communication ...
EWSN
2007
Springer
14 years 7 months ago
2007
Springer
Abstract. In this paper, we propose and evaluate RIDA, a novel informationdriven architecture for distributed data compression in a sensor network, allowing it to conserve energy a...
ISLPED
2009
ACM
14 years 2 months ago
2009
ACM
An energy efficient object recognition processor is proposed for real-time visual applications. Its energy efficiency is improved by lowering average power consumption while susta...
DAC
1997
ACM
13 years 12 months ago
1997
ACM
The InfoPad project was started at UC Berkeley in 1992 to investigate the issues involved in providing multimedia information access using a portable, wireless terminal. It quickl...