169 search results - page 12 / 34 » Low power architecture of the soft-output Viterbi algorithm |
DAC
2005
ACM
2005
ACM
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
14 years 8 months ago
To reduce power, Vdd programmability has been proposed recently to select Vdd-level for interconnects and to powergate unused interconnects. However, Vdd-level converters used in ...
FCCM
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper introduces the Low-Power Intelligent Tool Environment (LITE), an object oriented tool set designed for power visualization, analysis, and optimization. These tools lever...
CODES
2006
IEEE
14 years 1 months ago
2006
IEEE
Design of System-on-Chip (SoC) with regular mesh based Network-on-Chip (NoC) consists of mapping processing cores to routers, and routing of the traffic traces on the topology suc...
FPGA
2005
ACM
14 years 26 days ago
2005
ACM
Vdd-programmable FPGAs have been proposed recently to reduce FPGA power, where Vdd levels can be customized for different circuit elements and unused circuit elements can be powe...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
DPM (Dynamic Power Management) is an effective technique for reducing the energy consumption of embedded systems that is based on migrating to a low power state when possible. Whi...