331 search results - page 11 / 67 » Low power implementation of a turbo-decoder on programmable ... |
162
Voted
FPL
2005
Springer
15 years 11 months ago
2005
Springer
Domain-specific heterogeneous reconfigurable arrays provide high performance over generic Field Programmable Gate Arrays (FPGAs) while maintaining the flexibility for that particu...
ISCAS
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper proposes a low power commutator architecture based on triple port RAMs rather than dual port RAMs or conventional FIFO.forthe radix-4 pipelined FFTprocessor implementat...
212
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ANCS
2008
ACM
15 years 7 months ago
2008
ACM
Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Inte...
159
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VLSID
2007
IEEE
16 years 1 days ago
2007
IEEE
The 3-2, 4-2 and 5-2 compressors are the basic components in many applications, in particular partial product summation in multipliers. In this paper novel architectures and desig...
180
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CASES
2004
ACM
15 years 11 months ago
2004
ACM
Recognizing speech, gestures, and visual features are important interface capabilities for future embedded mobile systems. Unfortunately, the real-time performance requirements of...