331 search results - page 13 / 67 » Low power implementation of a turbo-decoder on programmable ... |
214
click to vote
ERSA
2009
15 years 3 months ago
2009
Medium-grain reconfigurable hardware (MGRH) architectures represent a hybrid between the versatility of a field programmable gate array (FPGA) and the computational power of a cust...
144
click to vote
ISCAS
2003
IEEE
15 years 11 months ago
2003
IEEE
— The authors present a number of complete cores which are specially tailored for the low power implementation of FIR filters executed using block processing. The paper reveals t...
155
click to vote
CHES
2004
Springer
15 years 11 months ago
2004
Springer
Since their publication in 1998, power analysis attacks have attracted significant attention within the cryptographic community. So far, they have been successfully applied to di...
180
click to vote
ICCAD
2002
IEEE
16 years 2 months ago
2002
IEEE
This paper describes an optimization technique able to optimize a complete wireless receiver architecture in a reasonable amount of time. The optimizer alternates between spice le...
146
click to vote
ISCAS
2007
IEEE
16 years 3 days ago
2007
IEEE
—This paper presents work on ultra-low-power circuits for brain–machine interfaces with applications for paralysis prosthetics, stroke, Parkinson’s disease, epilepsy, prosthe...