331 search results - page 29 / 67 » Low power implementation of a turbo-decoder on programmable ... |
179
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DAC
2004
ACM
16 years 6 months ago
2004
ACM
Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a sat...
174
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TVLSI
2008
15 years 5 months ago
2008
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
159
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VLSISP
2008
15 years 5 months ago
2008
ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
166
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JUCS
2007
15 years 5 months ago
2007
: The development of processors with full custom technology has some disadvantages, such as the time used to design the processors and the cost of the implementation. In this artic...
178
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PSB
2001
15 years 7 months ago
2001
This paper discusses the issues involved in implementing a dynamic programming algorithm for biological sequence comparison on a generalpurpose parallel computing platform based o...