331 search results - page 31 / 67 » Low power implementation of a turbo-decoder on programmable ... |
229
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ICES
2010
Springer
15 years 3 months ago
2010
Springer
Recently, a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an ef...
170
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JCM
2007
15 years 5 months ago
2007
— This paper reviews proposed realization concepts and achievements of wireless sensor nodes and focuses on new developments in the 24 GHz frequency range. The relatively high fr...
157
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DATE
2004
IEEE
15 years 9 months ago
2004
IEEE
When an application or external environmental conditions cause a chip's cooling capacity to be exceeded, dynamic thermal management (DTM) dynamically reduces the power densit...
137
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ARC
2009
Springer
15 years 10 months ago
2009
Springer
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
135
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ISCAS
2008
IEEE
16 years 9 days ago
2008
IEEE
—This paper presents three techniques to reduce the power consumption in ternary content-addressable memories (TCAMs). The first technique is to use newly developed monolithical...