331 search results - page 47 / 67 » Low power implementation of a turbo-decoder on programmable ... |
125
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IROS
2007
IEEE
16 years 3 days ago
2007
IEEE
— Many factors such as size, power, and weight constrain the design of modular snake robots. Meeting these constraints requires implementing a complex mechanical and electrical a...
167
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SPAA
2003
ACM
15 years 11 months ago
2003
ACM
We propose a new approach for constructing P2P networks based on a dynamic decomposition of a continuous space into cells corresponding to servers. We demonstrate the power of thi...
170
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ARITH
2001
IEEE
15 years 9 months ago
2001
IEEE
The Instruction Set Architecture (ISA) of a programmable processor is the native languageof the machine. It defines the set of operations and resourcesthat are optimized for that ...
157
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DATE
2004
IEEE
15 years 9 months ago
2004
IEEE
The MultiNoC system implements a programmable onchip multiprocessing platform built on top of an efficient, low area overhead intra-chip interconnection scheme. The employed inter...
155
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DAC
1994
ACM
15 years 10 months ago
1994
ACM
Asynchronous circuits are crucial in designing low power and high performance digital systems. In this paper, we present an ecient modular partitioning approach for asynchronous c...