331 search results - page 58 / 67 » Low power implementation of a turbo-decoder on programmable ... |
184
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ARITH
2005
IEEE
15 years 11 months ago
2005
IEEE
The floating-point unit in the Synergistic Processor Element of the 1st generation multi-core CELL Processor is described. The FPU supports 4-way SIMD single precision and intege...
213
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ECBS
1996
IEEE
15 years 10 months ago
1996
IEEE
In this paper, it is shown that, through the use of Model-Integrated Program Synthesis MIPS, parallel real-time implementations of image processing data ows can be synthesized fro...
158
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DATE
2010
IEEE
15 years 4 months ago
2010
IEEE
— Applications like 4G baseband modem require single-chip implementation to meet the integration and power consumption requirements. These applications demand a high computing pe...
173
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ISCA
2006
IEEE
15 years 11 months ago
2006
IEEE
Improvements in semiconductor technology have made it possible to include multiple processor cores on a single die. Chip Multi-Processors (CMP) are an attractive choice for future...
139
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CF
2006
ACM
15 years 11 months ago
2006
ACM
In this paper, we present a nano-scale reconfigurable mesh that is interconnected with ferromagnetic spin-wave buses. The architecture described here, while requiring the same num...