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ISCA
2012
IEEE
234views Hardware» more  ISCA 2012»
13 years 8 months ago
PARDIS: A programmable memory controller for the DDRx interfacing standards
Modern memory controllers employ sophisticated address mapping, command scheduling, and power management optimizations to alleviate the adverse effects of DRAM timing and resource...
Mahdi Nazm Bojnordi, Engin Ipek
ISLPED
1998
ACM
84views Hardware» more  ISLPED 1998»
15 years 10 months ago
Low power architecture of the soft-output Viterbi algorithm
CT This paper investigates the low power implementation issues of the soft-output Viterbi algorithm (SOVA), a building block for turbo codes. By briefly explaining the theory of t...
David Garrett, Mircea R. Stan
ICIP
1999
IEEE
16 years 7 months ago
Programmable Hardware Implementation for the Median-Rational Hybrid Filters
The Median-Rational Hybrid Filter (MRHF) has been recently introduced [1][2] as a new class of nonlinear filters and successfully applied to image filtering problems. The main cha...
Lazhar Khriji, Giuseppe Bernacchia, Moncef Gabbouj...
CORR
2010
Springer
89views Education» more  CORR 2010»
15 years 5 months ago
Power optimized programmable embedded controller
Now a days, power has become a primary consideration in hardware design, and is critical in computer systems especially for portable devices with high performance and more functio...
M. Kamaraju, K. Lal Kishore, A. V. N. Tilak
BIOADIT
2004
Springer
15 years 11 months ago
A Hardware Implementation of a Network of Functional Spiking Neurons with Hebbian Learning
Abstract. In this paper we present a functional model of a spiking neuron intended for hardware implementation. Some features of biological spiking neuabstracted, while preserving ...
Andres Upegui, Carlos Andrés Peña-Re...