55 search results - page 4 / 11 » Low power implementation of high throughput FIR filters |
HIPEAC
2009
Springer
14 years 1 months ago
2009
Springer
In this article, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating with a subthreshold supply voltage, which is below the voltage that tur...
VLSISP
1998
13 years 6 months ago
1998
This paper describes the architecture and the performance of a new programmable 16-bit Digital Signal Processor (DSP) engine. It is developed specifically for next generation wire...
ASPDAC
2007
ACM
13 years 10 months ago
2007
ACM
- This paper presents a real time programmable irregular Low Density Parity Check (LDPC) Encoder as specified in the IEEE P802.16E/D7 standard. The encoder is programmable for fram...
WCE
2007
13 years 7 months ago
2007
—The JPEG 2000 image coding standard employs the biorthogonal 9/7 wavelet for lossy compression. The performance of hardware implementation of 9/7-filter bank depends on accuracy...
VLSISP
2010
13 years 5 months ago
2010
Abstract Polyphase channelizer is an important component of subband adaptive filtering systems. This paper presents an energy-efficient hardware architecture and VLSI implementatio...