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» Low power implementation of high throughput FIR filters
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ASPDAC
2011
ACM
215views Hardware» more  ASPDAC 2011»
12 years 10 months ago
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture
—This paper presents an asynchronous FPGA that combines four-phase dual-rail encoding and LEDR (Level-Encoded Dual-Rail) encoding. Four-phase dual-rail encoding is used for small...
Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama...
TON
2010
151views more  TON 2010»
13 years 1 months ago
Throughput Optimal Distributed Power Control of Stochastic Wireless Networks
The Maximum Differential Backlog (MDB) control policy of Tassiulas and Ephremides has been shown to adaptively maximize the stable throughput of multihop wireless networks with ran...
Yufang Xi, Edmund M. Yeh
ICIP
1999
IEEE
14 years 8 months ago
Programmable Hardware Implementation for the Median-Rational Hybrid Filters
The Median-Rational Hybrid Filter (MRHF) has been recently introduced [1][2] as a new class of nonlinear filters and successfully applied to image filtering problems. The main cha...
Lazhar Khriji, Giuseppe Bernacchia, Moncef Gabbouj...
BMCBI
2010
151views more  BMCBI 2010»
13 years 6 months ago
Data reduction for spectral clustering to analyze high throughput flow cytometry data
Background: Recent biological discoveries have shown that clustering large datasets is essential for better understanding biology in many areas. Spectral clustering in particular ...
Habil Zare, Parisa Shooshtari, Arvind Gupta, Ryan ...
ICCAD
1994
IEEE
90views Hardware» more  ICCAD 1994»
13 years 10 months ago
Algorithm selection: a quantitative computation-intensive optimization approach
Given a set of specifications for a targeted application, algorithm selection refers to choosing the most suitable algorithm for a given goal, among several functionally equivalen...
Miodrag Potkonjak, Jan M. Rabaey