1004 search results - page 39 / 201 » Low power methodology and design techniques for processor de... |
HIPEAC
2007
Springer
14 years 2 months ago
2007
Springer
Voltage scaling reduces leakage power for cache lines unlikely to be referenced soon. Partitioning reduces dynamic power via smaller, specialized structures. We combine approaches,...
CASES
2006
ACM
14 years 2 months ago
2006
ACM
Rising interest in the applications of wireless sensor networks has spurred research in the development of computing systems for lowthroughput, energy-constrained applications. Un...
IBMRD
2006
13 years 8 months ago
2006
Because they are based on large content-addressable memories, load-store queues (LSQ) present implementation challenges in superscalar processors, especially as issue width and nu...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
Dynamic voltage scaling (DVS) is a well-known low power design technique that reduces the processor energy by slowing down the DVS processor and stretching the task execution time...
ISCA
2012
IEEE
11 years 11 months ago
2012
IEEE
Power consumption is a primary concern for microprocessor designers. Lowering the supply voltage of processors is one of the most effective techniques for improving their energy e...