1004 search results - page 8 / 201 » Low power methodology and design techniques for processor de... |
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
Abstract— In this paper, we present several techniques for lowpower design, including a descriptor-based low-power scheduling algorithm, design of dynamic voltage generator, and ...
ICIP
1999
IEEE
14 years 21 days ago
1999
IEEE
SBCCI
2003
ACM
14 years 1 months ago
2003
ACM
As we scale down to deep submicron (DSM) technology, noise is becoming a metric of equal importance as power, speed, and area. Smaller feature sizes, low voltage, and high frequen...
HPCA
2003
IEEE
14 years 8 months ago
2003
IEEE
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
VTS
2000
IEEE
14 years 24 days ago
2000
IEEE
1 At-speed testing is becoming increasingly difficult with external testers as the speed of microprocessors approaches the GHz range. One solution to this problem is built-in self-...