552 search results - page 16 / 111 » Low power techniques for Motion Estimation hardware |
PATMOS
2000
Springer
13 years 11 months ago
2000
Springer
Exploitation of data re-use in combination with the use of custom memory hierarchy that exploits the temporal locality of data accesses may introduce significant power savings, esp...
ISLPED
1999
ACM
14 years 1 days ago
1999
ACM
Modern microprocessors employ one or two levels of on-chip cachesto bridge the burgeoning speeddisparities between the processor and the RAM. These SRAM caches are a major source ...
DSD
2004
IEEE
13 years 11 months ago
2004
IEEE
Low power VLSI circuit design is one of the most important issues in present day technology. One of the ways of reducing power in a CMOS circuit is to reduce the number of transit...
APCCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— A data driven approach to design and optimization of low power combinational multipliers is presented. This technique depends on signal gating to avoid un-necessary computation...
ISCAS
2002
IEEE
14 years 20 days ago
2002
IEEE
Motion-threading is a novel technique that can efficiently incorporate motion information into the 3D wavelet video coding. By utilizing shape adaptive wavelet transform along wit...