552 search results - page 57 / 111 » Low power techniques for Motion Estimation hardware |
151
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ISLPED
2009
ACM
15 years 10 months ago
2009
ACM
We investigate techniques to design 45nm minimum-energy subthreshold CMOS circuits under timing constraints, considering the practical case of an 8-bit multiplier. We first show ...
116
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ISCAS
2005
IEEE
15 years 11 months ago
2005
IEEE
— A new architecture of a fractional-N phase-locked loop (PLL) frequency synthesizer is presented in this paper. The unique feature of the proposed frequency synthesizer is a loo...
165
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NSDI
2008
15 years 8 months ago
2008
Hidden malicious circuits provide an attacker with a stealthy attack vector. As they occupy a layer below the entire software stack, malicious circuits can bypass traditional defe...
160
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ISLPED
1997
ACM
15 years 9 months ago
1997
ACM
Significand pre-alignment is a pre requisite for floating point additions. This paper1 addresses the architectural design and energy delay evaluation of a Low Power Barrel Switch ...
183
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DAC
1997
ACM
15 years 10 months ago
1997
ACM
: Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power and cost goals. In t...