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TC
2008
13 years 7 months ago
Low-Transition Test Pattern Generation for BIST-Based Applications
A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during te...
Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed
ATS
2005
IEEE
191views Hardware» more  ATS 2005»
14 years 1 months ago
Low Transition LFSR for BIST-Based Applications
Abstract—This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within...
Mohammad Tehranipoor, Mehrdad Nourani, Nisar Ahmed
ICCD
2002
IEEE
108views Hardware» more  ICCD 2002»
14 years 4 months ago
Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding
Low power design techniques have been employed for more than two decades, however an emerging problem is satisfying the test power constraints for avoiding destructive test and im...
Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nic...
ISOLA
2010
Springer
13 years 5 months ago
Enforcing Applicability of Real-Time Scheduling Theory Feasibility Tests with the Use of Design-Patterns
Abstract. This article deals with performance verifications of architecture models of real-time embedded systems. We focus on models verified with the real-time scheduling theory...
Alain Plantec, Frank Singhoff, Pierre Dissaux, J&e...
ATS
2002
IEEE
108views Hardware» more  ATS 2002»
14 years 12 days ago
Fault Set Partition for Efficient Width Compression
In this paper, we present a technique for reducing the test length of counter-based pseudo-exhaustive built-in self-testing (BIST) based on width compression method. More formally...
Emil Gizdarski, Hideo Fujiwara