32 search results - page 3 / 7 » Low-level Benchmarking of a New Cluster Architecture |
FPL
1997
Springer
13 years 11 months ago
1997
Springer
We describe the capabilities of and algorithms used in a new FPGA CAD tool, Versatile Place and Route (VPR). In terms of minimizing routing area, VPR outperforms all published FPG...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
Modern design requirements have brought additional complexities to netlists and layouts. Millions of components, whitespace resources, and fixed/movable blocks are just a few to ...
SBACPAD
2005
IEEE
14 years 1 months ago
2005
IEEE
The time required to simulate a complete benchmark program using the cycle-accurate model of a microprocessor can be prohibitively high. One of the proposed methodologies, represe...
JMLR
2006
13 years 7 months ago
2006
An essential step in designing a new computer architecture is the careful examination of different design options. It is critical that computer architects have efficient means by ...
CF
2005
ACM
13 years 9 months ago
2005
ACM
Clustered processors lose performance as a result of clusteringinduced stalls. Such stalls are the result of distributed resources and cluster communication delays. Our performanc...