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» M-trie: an efficient approach to on-chip logic minimization
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CORR
2010
Springer
152views Education» more  CORR 2010»
13 years 4 months ago
Fault Tolerant Variable Block Carry Skip Logic (VBCSL) using Parity Preserving Reversible Gates
Reversible logic design has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power...
Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Z...
CORR
2010
Springer
152views Education» more  CORR 2010»
13 years 4 months ago
Evolutionary Approach to Test Generation for Functional BIST
In the paper, an evolutionary approach to test generation for functional BIST is considered. The aim of the proposed scheme is to minimize the test data volume by allowing the dev...
Y. A. Skobtsov, D. E. Ivanov, V. Y. Skobtsov, Raim...
ICCAD
2009
IEEE
101views Hardware» more  ICCAD 2009»
13 years 5 months ago
Compacting test vector sets via strategic use of implications
As the complexity of integrated circuits has increased, so has the need for improving testing efficiency. Unfortunately, the types of defects are also becoming more complex, which...
Nuno Alves, Jennifer Dworak, R. Iris Bahar, Kundan...
CONSTRAINTS
2007
112views more  CONSTRAINTS 2007»
13 years 7 months ago
Maxx: Test Pattern Optimisation with Local Search Over an Extended Logic
In the ECAD area, the Test Generation (TG) problem consists in finding an input vector test for some possible diagnosis (a set of faults) of a digital circuit. Such tests may have ...
Francisco Azevedo
RECOMB
2007
Springer
14 years 7 months ago
Association Mapping of Complex Diseases with Ancestral Recombination Graphs: Models and Efficient Algorithms
Association, or LD (linkage disequilibrium), mapping is an intensely-studied approach to gene mapping (genome-wide or in candidate regions) that is widely hoped to be able to effic...
Yufeng Wu