262 search results - page 4 / 53 » MAME: A Compression Function with Reduced Hardware Requireme... |
GRAPHICSINTERFACE
2004
13 years 8 months ago
2004
Today's hardware graphics accelerators incorporate techniques to antialias edges and minimize geometry-related sampling artifacts. Two such techniques, brute force supersampl...
TVLSI
2010
13 years 2 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
SACRYPT
2009
Springer
14 years 1 months ago
2009
Springer
Abstract. In this paper we analyse the security of the SHA-3 candidate ARIRANG. We show that bitwise complementation of whole registers turns out to be very useful for constructing...
ICISC
2008
13 years 8 months ago
2008
Hardware implementations of cryptographic algorithms are still vulnerable to side-channel attacks. Side-channel attacks that are based on multiple measurements of the same operatio...
ICCAD
2007
IEEE
13 years 11 months ago
2007
IEEE
Abstract-- In this paper, we propose a novel test data compression technique named CacheCompress, which combines selective encoding and dynamic dictionary based encoding. Depending...