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ACSD
2005
IEEE
90views Hardware» more  ACSD 2005»
14 years 1 months ago
Extensible and Scalable Time Triggered Scheduling
The objective of this paper is to present how to design a system that can accommodate additional functionality with either no changes to the design or adding architectural modules...
Wei Zheng, Jike Chong, Claudio Pinello, Sri Kanaja...
DATE
2009
IEEE
163views Hardware» more  DATE 2009»
13 years 11 months ago
Analysis and optimization of fault-tolerant embedded systems with hardened processors
1 In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques...
Viacheslav Izosimov, Ilia Polian, Paul Pop, Petru ...
ISCAS
2011
IEEE
261views Hardware» more  ISCAS 2011»
12 years 11 months ago
Optimization of area in digit-serial Multiple Constant Multiplications at gate-level
— The last two decades have seen many efficient algorithms and architectures for the design of low-complexity bit-parallel Multiple Constant Multiplications (MCM) operation, tha...
Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Pa...
DATE
2003
IEEE
123views Hardware» more  DATE 2003»
14 years 29 days ago
Parallel Processing Architectures for Reconfigurable Systems
Novel reconfigurable computing architectures exploit the inherent parallelism available in many signalprocessing problems. These architectures often consist of networks of compute...
Kees A. Vissers
IEEECIT
2010
IEEE
13 years 5 months ago
SESAM: An MPSoC Simulation Environment for Dynamic Application Processing
Future systems will have to support multiple and concurrent dynamic compute-intensive applications, while respecting real-time and energy consumption constraints. With the increase...
Nicolas Ventroux, Alexandre Guerre, Tanguy Sassola...