Actual graphic hardware becomes more and more powerful. Consequently, virtual scenes can be rendered in a very good quality integrating dynamic behavior, real-time shadows, bump m...
Recent probabilistic test generation approaches have proven that detecting single stuck-at faults multiple times is effective at reducing the defective part level (DPL). Unfortuna...
Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. R...
We propose a new approach to accelerate transaction level verification by raising the productivity of the verification suites including test patterns, protocol checker, and simula...
Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but al...
Ya-Lan Tsao, Ming Hsuan Tan, Jun-Xian Teng, Shyh-J...
We present a new conservative image-based occlusion culling method to increase the speed of hardware accelerated rendering of very complex general scenes which may consist of mill...
Heinrich Hey, Robert F. Tobler, Werner Purgathofer