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ICCAD
2009
IEEE
94views Hardware» more  ICCAD 2009»
15 years 2 months ago
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint
We propose a layout-driven test-architecture design and optimization technique for core-based system-on-chips (SoCs) that are fabricated using three-dimensional (3D) integration. ...
Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. ...
147
Voted
ICCV
2009
IEEE
15 years 2 months ago
Simultaneous alignment and clustering for an image ensemble
Joint alignment for an image ensemble can rectify images in the spatial domain such that the aligned images are as similar to each other as possible. This important technology has...
Xiaoming Liu 0002, Yan Tong, Frederick W. Wheeler
CORR
2010
Springer
152views Education» more  CORR 2010»
15 years 2 months ago
Fault Tolerant Variable Block Carry Skip Logic (VBCSL) using Parity Preserving Reversible Gates
Reversible logic design has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power...
Md. Saiful Islam 0003, Muhammad Mahbubur Rahman, Z...
IMCSIT
2010
15 years 1 months ago
Parallel, Massive Processing in SuperMatrix - a General Tool for Distributional Semantic Analysis of Corpus
The paper presents an extended version of the SuperMatrix system -- a general tool supporting automatic acquisition of lexical semantic relations from corpora. Extensions focus mai...
Bartosz Broda, Damian Jaworski, Maciej Piasecki
174
Voted
RFIDSEC
2010
14 years 11 months ago
EC-RAC: Enriching a Capacious RFID Attack Collection
Abstract. We demonstrate two classes of attacks on EC-RAC, a growing set of RFID protocols. Our first class of attacks concerns the compositional approach used to construct a parti...
Ton van Deursen, Sasa Radomirovic