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EH
1999
IEEE
179views Hardware» more  EH 1999»
13 years 11 months ago
Artificial Evolution of Active Filters: A Case Study
This article focuses on the application of artificial evolution to the synthesis of analog active filters. The main objective of this research is the achievement of a new class of...
Ricardo Salem Zebulum, Marco Aurélio Cavalc...
ISPD
2004
ACM
150views Hardware» more  ISPD 2004»
14 years 25 days ago
Topology optimization of structured power/ground networks
This paper presents an efficient method for optimizing the design of power/ground (P/G) networks by using locally regular, globally irregular grids. The procedure divides the pow...
Jaskirat Singh, Sachin S. Sapatnekar
DATE
2006
IEEE
140views Hardware» more  DATE 2006»
14 years 1 months ago
A hybrid framework for design and analysis of fault-tolerant architectures
It is anticipated that self assembled ultra-dense nanomemories will be more susceptible to manufacturing defects and transient faults than conventional CMOS-based memories, thus t...
Debayan Bhaduri, Sandeep K. Shukla, Deji Coker, Va...
DAC
2005
ACM
14 years 8 months ago
ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction
This paper presents an efficient hierarchical 3D capacitance extraction algorithm -- ICCAP. Most previous capacitance extraction algorithms introduce intermediate variables to fac...
Rong Jiang, Yi-Hao Chang, Charlie Chung-Ping Chen
ISLPED
1999
ACM
131views Hardware» more  ISLPED 1999»
13 years 11 months ago
Challenges in clockgating for a low power ASIC methodology
Gating the clock is an important technique used in low power design to disable unused modules of a circuit. Gating can save power by both preventing unnecessary activiiy in the lo...
David Garrett, Mircea R. Stan, Alvar Dean