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» Managing Pipeline-Reconfigurable FPGAs
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IPPS
2003
IEEE
14 years 10 days ago
Fast Online Task Placement on FPGAs: Free Space Partitioning and 2D-Hashing
Partial reconfiguration allows for mapping and executing several tasks on an FPGA during runtime. Multitasking on FPGAs raises a number of questions on the management of the reco...
Herbert Walder, Christoph Steiger, Marco Platzner
DELTA
2006
IEEE
13 years 10 months ago
Using Design Patterns to Overcome Image Processing Constraints on FPGAs
The mapping of image processing algorithms to hardware is complicated by several hardware constraints including limited processing time, limited access to data and limited resourc...
K. T. Gribbon, Donald G. Bailey, Christopher T. Jo...
CASES
2008
ACM
13 years 9 months ago
Dynamic coprocessor management for FPGA-enhanced compute platforms
Various commercial programmable compute platforms have their processor architecture enhanced with field-programmable gate arrays (FPGAs). In a common usage scenario, an applicatio...
Chen Huang, Frank Vahid
DATE
2003
IEEE
109views Hardware» more  DATE 2003»
14 years 10 days ago
Run-Time Management of Logic Resources on Reconfigurable Systems
Dynamically reconfigurable systems based on partial and dynamically reconfigurable FPGAs may have their functionality partially modified at run-time without stopping the operation...
Manuel G. Gericota, Gustavo R. Alves, Miguel L. Si...
FPL
2007
Springer
106views Hardware» more  FPL 2007»
14 years 1 months ago
RAMP Blue: A Message-Passing Manycore System in FPGAs
We are developing a set of reusable design blocks and several prototype systems for emulation of multi-core architectures in FPGAs. RAMP Blue is the first of these prototypes and...
Alex Krasnov, Andrew Schultz, John Wawrzynek, Greg...