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ISCA
2011
IEEE
294views Hardware» more  ISCA 2011»
13 years 2 months ago
Moguls: a model to explore the memory hierarchy for bandwidth improvements
In recent years, the increasing number of processor cores and limited increases in main memory bandwidth have led to the problem of the bandwidth wall, where memory bandwidth is b...
Guangyu Sun, Christopher J. Hughes, Changkyu Kim, ...
CVIU
2011
13 years 2 months ago
Graph-based quadratic optimization: A fast evolutionary approach
Quadratic optimization lies at the very heart of many structural pattern recognition and computer vision problems, such as graph matching, object recognition, image segmentation, ...
Samuel Rota Bulò, Marcello Pelillo, Immanue...
CADE
2011
Springer
12 years 10 months ago
Experimenting with Deduction Modulo
Deduction modulo is a generic framework to describe proofs in a theory better than using raw axioms. This is done by presenting the theory through rules rewriting terms and proposi...
Guillaume Burel
CCS
2011
ACM
12 years 10 months ago
Policy auditing over incomplete logs: theory, implementation and applications
We present the design, implementation and evaluation of an algorithm that checks audit logs for compliance with privacy and security policies. The algorithm, which we name reduce,...
Deepak Garg, Limin Jia, Anupam Datta
HIPEAC
2011
Springer
12 years 10 months ago
NoC-aware cache design for multithreaded execution on tiled chip multiprocessors
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
Ahmed Abousamra, Alex K. Jones, Rami G. Melhem