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CONCUR
2006
Springer
13 years 11 months ago
Sanity Checks in Formal Verification
One of the advantages of temporal-logic model-checking tools is their ability to accompany a negative answer to the correctness query by a counterexample to the satisfaction of the...
Orna Kupferman
FPGA
2000
ACM
141views FPGA» more  FPGA 2000»
13 years 11 months ago
Tolerating operational faults in cluster-based FPGAs
In recent years the application space of reconfigurable devices has grown to include many platforms with a strong need for fault tolerance. While these systems frequently contain ...
Vijay Lakamraju, Russell Tessier
LICS
1991
IEEE
13 years 11 months ago
Logic Programming in a Fragment of Intuitionistic Linear Logic
When logic programming is based on the proof theory of intuitionistic logic, it is natural to allow implications in goals and in the bodies of clauses. Attempting to prove a goal ...
Joshua S. Hodas, Dale Miller
ASPLOS
2010
ACM
13 years 10 months ago
Micro-pages: increasing DRAM efficiency with locality-aware data placement
Power consumption and DRAM latencies are serious concerns in modern chip-multiprocessor (CMP or multi-core) based compute systems. The management of the DRAM row buffer can signif...
Kshitij Sudan, Niladrish Chatterjee, David Nellans...
ICDE
2010
IEEE
206views Database» more  ICDE 2010»
13 years 9 months ago
HECATAEUS: Regulating Schema Evolution
HECATAEUS is an open-source software tool for enabling impact prediction, what-if analysis, and regulation of relational database schema evolution. We follow a graph theoretic appr...
George Papastefanatos, Panos Vassiliadis, Alkis Si...