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DAC
2007
ACM
14 years 9 months ago
Reducing Data-Memory Footprint of Multimedia Applications by Delay Redistribution
It is now common for multimedia applications to be partitioned and mapped onto multiple processing elements of a system-on-chip architecture. An important design constraint in suc...
Balaji Raman, Samarjit Chakraborty, Wei Tsang Ooi,...
HPCA
2011
IEEE
13 years 13 days ago
Essential roles of exploiting internal parallelism of flash memory based solid state drives in high-speed data processing
Flash memory based solid state drives (SSDs) have shown a great potential to change storage infrastructure fundamentally through their high performance and low power. Most recent ...
Feng Chen, Rubao Lee, Xiaodong Zhang
ICCAD
2006
IEEE
111views Hardware» more  ICCAD 2006»
14 years 5 months ago
Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs
This work describes a new mapping technique, RAM-MAP, that identifies parts of circuits that can be efficiently mapped into the synchronous embedded memories found on field prog...
Gordon R. Chiu, Deshanand P. Singh, Valavan Manoha...
IPPS
1999
IEEE
14 years 1 months ago
Shuffle Memory System
This paper proposes a new memory system called shuffle memory. The shuffle memory is a generalization of transposition memory that has been widely used in 2-D Discrete Cosine Tran...
Kichul Kim
JUCS
2006
112views more  JUCS 2006»
13 years 8 months ago
A Multi-objective Genetic Approach to Mapping Problem on Network-on-Chip
Abstract: Advances in technology now make it possible to integrate hundreds of cores (e.g. general or special purpose processors, embedded memories, application specific components...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi