85 search results - page 12 / 17 » Mapping Interconnection Networks into VEDIC Networks |
ISLPED
2005
ACM
14 years 1 months ago
2005
ACM
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
FPGA
2004
ACM
14 years 1 months ago
2004
ACM
In this paper, an efficient implementation of a high performance coarse-grain reconfigurable data-path on a mixed-granularity reconfigurable platform is presented. It consists of ...
IJCAI
1997
13 years 9 months ago
1997
This paper describes an evolvable hardware (EHW) system for generalized neural network learning. We have developed an ASIC VLSI chip, which is a building block to configure a scal...
TSP
2008
13 years 7 months ago
2008
Abstract--A method for the computation of nonlinear digital filter networks containing delay-free loops is proposed. By preserving the topology of the network this method permits t...
ICPADS
2006
IEEE
14 years 1 months ago
2006
IEEE
Congestion management is likely to become a critical issue in interconnection networks, as increasing power consumption and cost concerns will lead to the use of smaller networks....