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» Mapping Interconnection Networks into VEDIC Networks
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IJCNN
2008
IEEE
14 years 1 months ago
Wafer-scale integration of analog neural networks
Abstract— This paper introduces a novel design of an artificial neural network tailored for wafer-scale integration. The presented VLSI implementation includes continuous-time a...
Johannes Schemmel, Johannes Fieres, Karlheinz Meie...
IPPS
1996
IEEE
13 years 11 months ago
Partitionability of the Multistage Interconnection Networks
- Partitionability allows the creation of many physically independent subsystems, each of which retains an identical functionality as its parent network and has no communication in...
Yeimkuan Chang
SC
2009
ACM
14 years 1 months ago
Scalable computing with parallel tasks
Recent and future parallel clusters and supercomputers use SMPs and multi-core processors as basic nodes, providing a huge amount of parallel resources. These systems often have h...
Jörg Dümmler, Thomas Rauber, Gudula R&uu...
EUROPAR
2005
Springer
14 years 16 days ago
Cost / Performance Trade-Offs and Fairness Evaluation of Queue Mapping Policies
Whereas the established interconnection networks (ICTN) achieve low latency by operating in the linear region, i.e. oversizing the fabric, the recent strict cost and power constrai...
Teresa Nachiondo Frinós, Jose Flich, Jos&ea...
DATE
2007
IEEE
118views Hardware» more  DATE 2007»
14 years 1 months ago
Statistical model order reduction for interconnect circuits considering spatial correlations
In this paper, we propose a novel statistical model order reduction technique, called statistical spectrum model order reduction (SSMOR) method, which considers both intra-die and...
Jeffrey Fan, Ning Mi, Sheldon X.-D. Tan, Yici Cai,...