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PODC
2009
ACM
14 years 8 months ago
Load balancing without regret in the bulletin board model
We analyze the performance of protocols for load balancing in distributed systems based on no-regret algorithms from online learning theory. These protocols treat load balancing a...
Éva Tardos, Georgios Piliouras, Robert D. K...
DAC
2009
ACM
14 years 2 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
ISPD
2003
ACM
133views Hardware» more  ISPD 2003»
14 years 27 days ago
Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time
In 21st-Century VLSI design, clocking plays crucial roles for both performance and timing convergence. Due to their non-convex nature, optimal minimum-delay/area zero-skew wire-si...
Jeng-Liang Tsai, Tsung-Hao Chen, Charlie Chung-Pin...
ICUIMC
2011
ACM
12 years 11 months ago
Opportunities of MIM capture in IEEE 802.11 WLANs: analytic study
Physical layer capture in WLANs makes a receiver to decode a relatively strong packet in a collision. According to recent works, an augmented physical layer capture handles interf...
Joonsoo Lee, Young-myoung Kang, Suchul Lee, Chong-...
VIS
2004
IEEE
164views Visualization» more  VIS 2004»
14 years 8 months ago
Real-Time Motion Estimation and Visualization on Graphics Cards
We present a tool for real-time visualization of motion features in 2D image sequences. The motion is estimated through an eigenvector analysis of the spatiotemporal structure ten...
Christoph S. Garbe, Robert Strzodka