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» Massively parallel processing on a chip
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DATE
2006
IEEE
88views Hardware» more  DATE 2006»
14 years 1 months ago
Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures
Temporal partitioning techniques are useful to implement large and complex applications, which can be split into partitions in FPGA devices. In order to minimize resources, each o...
Paulo Sérgio B. do Nascimento, Manoel Euseb...
CLUSTER
2008
IEEE
14 years 2 months ago
A multicore-enabled multirail communication engine
—The current trend in clusters architecture leads toward a massive use of multicore chips. This hardware evolution raises bottleneck issues at the network interface level. The us...
Elisabeth Brunet, François Trahay, Alexandr...
ICDCS
1995
IEEE
13 years 11 months ago
MASSIVE: A Distributed Virtual Reality System Incorporating Spatial Trading
MASSIVE is a distributed virtual reality system. It provides rich facilities to support user interaction and cooperation via text, audio and graphics media, and interaction is con...
Chris Greenhalgh, Steve Benford
DATE
2002
IEEE
103views Hardware» more  DATE 2002»
14 years 14 days ago
Communication Mechanisms for Parallel DSP Systems on a Chip
We consider the implication of deep sub-micron VLSI technology on the design of communication frameworks for parallel DSP systems-on-chip. We assert that distributed data transfer...
Joseph Williams, Nevin Heintze, Bryan D. Ackland
DAC
2009
ACM
14 years 2 months ago
PiCAP: a parallel and incremental capacitance extraction considering stochastic process variation
It is unknown how to include stochastic process variation into fast-multipole-method (FMM) for a full chip capacitance extraction. This paper presents a parallel FMM extraction us...
Fang Gong, Hao Yu, Lei He