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» Massively parallel processing on a chip
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VLSID
2007
IEEE
133views VLSI» more  VLSID 2007»
14 years 8 months ago
On the Impact of Address Space Assignment on Performance in Systems-on-Chip
Today, VLSI systems for computationally demanding applications are being built as Systems-on-Chip (SoCs) with a distributed memory sub-system which is shared by a large number of ...
G. Hazari, Madhav P. Desai, H. Kasture
ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
14 years 4 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
HICSS
2009
IEEE
106views Biometrics» more  HICSS 2009»
14 years 2 months ago
A Radical Approach to Network-on-Chip Operating Systems
Operating systems were created to provide multiple tasks with access to scarce hardware resources like CPU, memory, or storage. Modern programmable hardware, however, may contain ...
Michael Engel, Olaf Spinczyk
TVLSI
2008
85views more  TVLSI 2008»
13 years 7 months ago
Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors
Chip-Multi-Processors (CMP) utilize multiple energy-efficient Processing Elements (PEs) to deliver high performance while maintaining an efficient ratio of performance to energy-c...
A. Elyada, Ran Ginosar, Uri Weiser
OSDI
1994
ACM
13 years 9 months ago
Distributed Filaments: Efficient Fine-Grain Parallelism on a Cluster of Workstations
A fine-grain parallel program is one in which processes are typically small, ranging from a few to a few hundred instructions. Fine-grain parallelism arises naturally in many situ...
Vincent W. Freeh, David K. Lowenthal, Gregory R. A...